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c op y r i ght ? r d a m i cr o el ect r o n i cs i n c. 2006. a l l r i g h t s ar e r eser ved . the information contained herein is the exclusive proper ty of rda and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of rda . rda 58 0 7 f p s i ng l e -c h i p b r o ad c as t f m r ad i o t une r re v .1.2? a pr i l .2012 1 g eneral d es cr i p t i o n t he r d a 5 807fp series is the new est generation single - chip broadcast fm stereo radio tuner with fully integrated synthesizer, if selectivity , rds/rbds and mp x decoder. the tuner uses the cmos process, support multi - interface and require the least external component. the package sizes is sop16 . it is completely adjustment - free. all these make it very suitable for portable devices. t he r d a 58 07f p series has a pow erful low - if digital audio processor, this make it have optimum sound quality with varying reception conditions. t he r d a 5 807fp series support frequency range is from 50 mhz to 11 5mhz. 1. 1 f eat u r es ? c mo s si ngle - chip fully - integrated fm tuner ? low pow er consumpt ion ? t ot al c urrent co nsumption lower than 2 0 ma at 3. 0 v power supply when under normal situation ? s up por t worldwide frequency band ? 50 - 1 08 mhz ? s up por t flexible channel spacing mode ? 100 k h z , 200khz, 50khz and 25khz ? s u p p ort rds/rbds ? d ig it a l lo w - if tuner ? i m a ge - re ject down - converter ? h i g h p erformance a/d converter ? i f s e lectivity performed internally ? f ul l y integrated digital frequency synthesizer ? f ul l y integrated on - chip rf and if vco ? f ul l y integrated on - chip loop filter ? a ut on om ous search tuning ? s up por t 32.768khz cry stal oscillator ? d i gi t al auto gain control (agc) ? d i gi t al adaptive noise cancellation ? mo n o / stereo switch ? s o f t m u te ? h i g h c ut ? p r og r ammable de - emphasis (50/75 s) ? r ec ei v e signal strength indicator (rssi) and snr ? b a ss b o o st ? v ol um e c ontrol and mute ? i 2 ? li ne - l evel analog output voltage s digital ou t p ut i nt er f ac e ? 32. 76 8 k h z 12m,24m,13m,26m,19.2m,38.4mhz r ef e r e nc e c l oc k ? o nl y s upport 2 - wire bus interface ? d i r ec tly support 32 resistance loading ? i nt egr at ed ldo regulator ? 2 .7 t o 3.3 v operation voltage ? so p1 6 package . figure1 - 1. r d a 5807f p top view rda 5807 fp 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 g p io 2 g p io 3 g nd ro ut lo ut rcl k v dd g nd g p io 1 g nd rf g nd fm i n g nd g nd s clk s da http://
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 2 of 23 1.2 appli cations ? cellular handsets ? mp3, mp4 players ? portable radios ? pdas, noteboo k
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 3 of 23 2 table of contents 1 general description .................................................................................................................................... 1 1.1 featur es ................................................................................................ ................................ ......... 1 1.2 a pplic a ti o n s .................................................................................................................................... 2 2 table of contents ......................................................................................................................................... 3 3 functional description ................................ ................................ ................................ ................................ 4 3.1 f m r ecei v er ................................ ................................ ................................ ................................ .. 4 3.2 s y nthes i zer ................................................................................................ ................................ .... 4 3.3 p ow e r s up pl y ................................................................................................................................ 4 3 .4 r e s e t a nd c ontrol i nt er f ace s el ect ................................ ................................ ............................. 4 3.5 c ont r ol i nt e r f ace ................................................................................................ ........................... 5 3.6 i 2 s a udi o d at a i nt erface ............................................................................................................... 5 3 .7 gpio outputs ................................................................................................................................ 5 4 e l ect rical ch ar a ct eri s t i cs ................................ ................................ ................................ ........................... 6 5 receiver characteristics ................................................................ ................................ ............................. 7 6 serial interface ............................................................................................................................................ 8 6.1 i 2 c interface timing ................................ ................................ ................................ ...................... 8 7 r egister def in it ion ................................ ................................ ................................ ................................ ...... 9 8 p ins d e s c r ip t ion ................................ ................................ ................................ ................................ ......... 15 9 a p plicat ion d iag r am ................................ ................................ ................................ ................................ . 17 9.1 r d a 5807fp c om m on a ppl i c a t i on : ................................ ................................ ........................... 17 9.1.1 b ill of m a te r ia ls : ................................ ................................ ................................ ......................... 17 10 p h ys ic al d im e n s ion ................................................................ ................................ ................................... 18 11 p c b l and p at te r n ................................ ................................ ................................ ................................ . 19 12 c ha nge li s t ................................ ................................ ................................ ................................ ................ 22 c on ta c t in f or m ation ................................ ................................ ................................ ................................ ......... 23
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 4 of 23 3 functional description i adc l dac r dac q adc + - audio dsp core digital filter mpx decoder stereo/mono audio vco synthesizer gpio interface bus rssi sdio sclk mcu gpio rda 5807fp lout rout fmin rclk 2 . 7 - 3 . 3 v 32.768 khz vdd ldo limiter lna i pga q pga rds / rbds f i gur e 3 - 1 . r d a 5 807f p f m t uner b l oc k d i agr am 3 .1 f m r ecei v er t he r ec ei v er us es a di gi t al l o w - i f ar c h i t ec t ur e t h at av o i ds t he di f f i c ul t i es a s s oc i at ed w i t h d i r ec t c onv er s i on w h i l e de l i v er i n g l o w er s ol ut i on c os t and r educ es c om pl ex i t y , and i n t egr a t es a l o w noi s e am pl i f i er ( ln a ) s up por t i ng t he f m br oadc as t b and ( 50 t o 1 15 mh z ) , a m u lt i - ph as e i m age - r ej ec t m i x er ar r a y , a pr o gr am m abl e ga i n c ont r ol ( p g a ) , a h i gh r es o l ut i on an al o g - to - d ig it a l c onv er t er s ( a d c s ) , an au di o d s p and a h i gh - f i del i t y di gi t a l - to - a na l og c o n v er t er s ( d a c s ) . t he lim i t er pr e v e nt s o v er l oad i ng a nd l i m i t s t he am ount of i nt er m odul a t i o n pr oduc t s c r eat ed b y s t r ong adj ac e nt c ha nne l s . t he m ul t i - phase mixer array down converts the lna output differential rf signal to low - if, it also has image - reject function and harmonic tones rejection . t he p g a amplifies the mixer output if signal and then digitized with adcs. t he d s p core finishes the channel selection, fm demodulation, stereo mpx decoder and out put audio signal. the mpx decoder can autonomous switch from stereo to mono to limit the output noise. t he d a c s convert digital audio signal to analog and change the volume at same time. the dacs has low - pass feature and - 3db frequency is about 30 khz . 3. 2 s yn thesizer t he f r equenc y synthesizer generates the local oscillator s ignal which divide to multi - phase , then be used to downconvert the rf input to a constant low intermediate frequency (if). the synthesizer reference clock is 32.768 khz . t he s y nt hesizer fre quency is defined by bits chan [9:0] with the range from 50 mhz to 115 mhz. 3. 3 powe r s u p p l y t he r d a 5807fp integrated one ldo which suppl ies power to the chip. t he external supply voltage range is 2.7 - 3.3 v. 3. 4 r e set and control interface select t he r d a 58 07f p is r e s e t i t s el f w hen v d d is p o w er up. a nd al s o s u ppo r t s o ft r es et b y t r i g ger 02h b i t 1 from 0 to 1 . t he RDA5807FP only support i 2 c control interface bus mode.
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 5 of 23 3.5 control interface the RDA5807FP only supports i 2 the i c control i nt er f ac e. 2 c interface is compliant to i 2 c b us specification 2.1. it includes two pins: sclk and sdio. a i 2 c i nt er f ac e t r ans f er begi ns w i t h s t a r t c ondi t i o n, a c om m and b y t e and dat a b y t es , eac h b y t e h as a f ol l o w ed a c k ( o r n a c k ) bi t , a nd en ds w i t h s t o p c ond i t i on. t he c om m and b y t e i nc l ude s a 7 - bi t c h i p a ddr es s ( 001 0 000b) a nd a r / w b i t. t he a c k ( or n a c k ) i s al w a y s s e nt ou t b y r ec e i v er . w h en i n w r i t e t r ans f er , d at a b y t es i s w r i t t en out f r o m mc u , and w h en i n r e ad t r a ns f er , dat a b y t es i s r ead out f r om r d a 5807 f p . t her e i s no v i s i b l e register addre ss in i 2 c interface transfers. the i 2 3.6 i c interface has a fixed start register address ( 0x 02h for write transfer and 0x 0ah for read transfer), and an internal incremental address counter. if register address meets the end of register file, 0x 3a h, register add ress will wrap back to 0x 00h. for write transfer, mcu programs registers from register 0x 02h high byte, then register 0x 02h low byte, then register 0x 03h high byte, till the last register. RDA5807FP always gives out ack after every byte, and mcu gives out stop condition when register programming is finished. for read transfer, afte r command byte from mcu, RDA5807FP sends out register 0x 0ah high byte, then register 0x 0ah low byte, then register 0x 0bh high byte, till receives nack from mcu. mcu gives out ack for data bytes besides last data byte. mcu gives out n a c k f or l as t da t a b y t e, and t hen r d a 5 807f p w i l l r e t ur n t he bus t o m c u , a nd mc u w il l g iv e o u t s t o p c o n d it io n . 2 the RDA5807FP support s i s audio data interface 2 s ( i n t er _i c s o und bus) audio interface. the interface is fully compliant with i 2 s bus specification. when setting i2sen bit high, RDA5807FP will output sck, ws, sd signals from gpio3, gpio1, gpio2 as i 2 s m a s t er and t r ans m i t t er , t he s am pl e r at e i s 4 8 k b ps 44. 1k bp s , 32k bp s ?. . r d a 58 07f p al s o s uppor t as i 2 3. 7 gpio outputs s s l a v er m ode and t r a ns m i t t er , t he s a m pl e r at e i s l es s t han 10 0k bp s . t he RDA5807FP has three gpios. the function of gpios could programmed with bits gpio1[1:0], gpio2[1:0], gpio3[1:0] and i2sen. i f i 2s e n i s s et t o l o w , g p i o pi ns c oul d be pr ogr am m ed t o out p ut l o w or hi g h or h i gh - z , or be pr ogr am m ed t o out p ut i nt er r u pt and s t er e o i nd i c at or w i t h bi t s g p i o 1[ 1: 0] , g p i o 2[ 1: 0] , g p i o 3[ 1: 0] . g p i o 2 c oul d be pr ogr am m ed t o out p ut a l o w i nt er r u pt ( i nt er r upt w i l l b e g ener a t ed onl y w i t h i nt er r u pt en ab l e b i t s t c i e n i s s et t o hi gh) w hen s eek / t une pr oc es s c om pl et es . g p i o 3 c oul d be programmed to output stereo indicator bit st. c ons t ant l o w , hi gh or h i gh - z f unc t i on al i t y i s av a i l ab l e r e gar d l es s of t he s t at e of v d d s u p p lie s or t he e n a b le bi t . sc k m sb sd w s 1 sck left channel l sb msb 1 sck ri g h t ch a n n e l l sb f i gur e 3- 2 i 2s d i gi t a l a udi o f or m a t
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 6 of 23 4 electrical char acteristics table 4 - 1 dc electrical s pecification (recommended operation conditions): symbol description min typ max unit vdd supply voltage 2.7 3.0 3. 3 v t ambient temperature amb - 2 0 2 7 +7 5 v cmos low level input voltage il 0 0.3*v dd v v cmos high level input voltage ih 0.7*v dd v dd v v cmos threshold voltage th 0.5* v dd v table 4 - 2 dc electrical specification (absolute maximum ratings): s ymbol description min typ max unit t ambient temperature amb - 40 +90 c i input current in - 10 ( 1) +10 ma v input voltage in - 0.3 (1) v dd +0.3 v v lna fm input leve l lna +10 dbm notes: 1. for pin: sclk, sdio table 4 - 3 power c onsumption s pecification (v dd = 3.0 v, t a = 25 , unless otherwise specified) symbol description condition typ unit i supply current vdd enable=1 (1) 20 ma i supply current vdd enable=1 (2 ) 2 1 ma i powerdown current pd enable=0 2 5 a notes: 1. for strong input signal condition 2. for weak input signal conditi on
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 7 of 23 5 receiver characteristics table 5 - 1 receiver characteristics ( v dd = 3 v, t a = 25 c, unless otherwise specified) symbol parameter conditions min typ max unit general specifications f fm i nput f requency range in adjust band register 50 115 mhz v sensitivity rf s /n=26db 1,2,3 50 mhz - 1 .4 1. 8 v emf 65 mhz - 1.2 1.5 88mhz - 1.2 1.5 98mhz - 1.3 1.5 108mhz - 1.3 1.5 115mhz - 1.3 1. 8 ip3 input ip3 in agcd=1 4 80 - - db v a m suppression am m = 0.3 1,2 60 - - db s adjacent channel selectivity 200 200khz 50 70 - db s 400khz selectivity 400 400khz 60 85 - db v afl ; v audio l/r output voltage afr (pins lout and rout) 1,2 volume [3:0] =1111 - 36 0 - mv s/ n maximum signal to noise ratio 1,2,3,5 mono 55 2 57 - db stereo 53 6 55 - stereo channel separation scs 35 - - db r a udi o o ut put load i ng resistance l single - ended 32 - - t hd a udi o t ot a l h ar m oni c distortion volume [3:0] =1111 1,3,6 r load - =1k 0. 15 0. 2 % r load - =32 0.2 - a udi o o ut put l/ r imbalance aoi 1,6 - - 0. 05 db r mute attenuation ratio mute volume[3:0]=0000 1 60 - - db bw audio response audio 1khz=0db 3 db point 1 low freq - 9 100 - hz high freq - 14 - pi n s f mi n , l o ut , ro ut v pins fmin input common mo de voltage com_rfin 0 v v a udi o o ut put c o m m on m ode voltage com 8 1.0 1. 05 1. 1 v no tes: 1. f in =6 5 to 1 15 mhz; f mod 2 . ? f=22.5khz ; 3. b =1khz; de - emphasis=75 s; mono=1; l=r unless noted otherwise; af = 30 0 h z t o 1 5 k h z , r b w < = 10 h z ; 4. | f 2 - f 1 |>1mhz, f 0 =2xf 1 - f 2 , agc disable, f in 5. p = 76 to 108mhz ; rf =60db u v; 6 . ? f= 7 5k h z , f pi l o t = 10 % 7. m eas ured at v emf = 1 m v, f rf 8. at lout and rout p i n s 9 . a d j u s t a bl e = 65 t o 1 08 m h z
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 8 of 23 6 serial interface 6.1 i 2 table 6 - 1 i c interface t iming 2 ( v dd = 3.0 v , t c interface t iming c haracteristics a = 25 c, unless otherwise specified) parameter symbol test condition min typ max unit sclk frequency f scl 0 - 400 khz sclk high time t high 0.6 - - s sclk low time t low 1.3 - - s setup time for start condition t su:sta 0.6 - - s hold time for start condition t hd:sta 0.6 - - s setup time for stop c ondition t su:sto 0.6 - - s sdio input to sclk setup t su:dat 100 - - ns sdio input to sclk hold t hd:dat 0 - 900 ns stop to start time t buf 1.3 - - s sdio output fall time t f:out 20+0.1c - b 250 ns sdio input, sclk rise/fall time t r:in / t f:in 20+0.1c - b 300 ns input spike suppression t sp - - 50 ns sclk, sdio capacitive loading c b - - 50 pf digital input pin capacitance 5 pf sclk sdio 1 - 7 8 9 1-7 8 9 1 - 7 8 9 start ack data high byte ack r / w address data low byte ack stop t su : sta t hd : sta t sp start t su :sto t buf t su : dat t hd : dat fi gur e 6 - 1 . i 2 c i nt er f ac e w r i t e t i m i ng d i agr am sclk sdio 1 - 7 8 9 1 - 7 8 9 1- 7 8 9 start ack data high byte ack r / w address data low byte nack stop t sp start t buf t su :sta t hd:sta t su:dat t hd:dat t su :sto figure 6 - 2 . i 2 c i nt er f ac e r e ad t i m i ng d i agr am
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 9 of 23 7 register definition reg bits name function default 00h 15:8 chipid[7:0] chip id. 0x 58 02h 15 dhiz audio output high - z disable. 0 = high impedance; 1 = normal operation 0 14 dmute mute disable. 0 = mute; 1 = normal oper ation 0 13 mono mono select. 0 = stereo; 1 = force mono 0 12 bass bass boost. 0 = disabled; 1 = bass boost enabled 0 11 rclk n on - calibrate mode 0=rclk clock is always supply 1=rclk clock is not always supply when fm w ork ( when 1, RDA5807FP can ? t dir ectly support - 20 ~70 temperature. only suppory 20 temperature swing from tune point ) 0 10 rclk direct input mode 1=rclk clock use the directly input mode 0 9 seekup seek up. 0 = seek down; 1 = seek up 0 8 seek seek. 0 = disable stop seek; 1 = enable seek begins i n the direction specified by s e e kup a nd e n ds w he n a c ha nne l i s f ound , o r t h e en t i r e b a n d h as b een sea r ch ed . the seek bit is set low and the stc bit is set high when the seek operation completes. 0 7 skmode seek mode 0 = wrap at the upper or lower band l imit and continue seeking 1 = st o p seeki n g at t h e u p p er o r l o w er b an d limit 0 6:4 clk_mode[2:0] 000=32.768khz 001=12mhz 101=24mhz 010=13mhz 110=26mhz 011=19.2mhz 111=38.4mhz 000 3 rds_en rds/rbds enable i f 1, rds/rbds enable 0 2 new_method new demodu late method enable, can improve the receive sensitivity about 1db. 0 1 soft_reset soft reset. if 0, not reset; if 1, reset. 0
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 10 of 23 reg bits name function default 0 enable power up enable. 0 = disabled; 1 = enabled 0 03h 15: 6 chan[ 9 :0] channel select. band = 0 f r eq u en cy = channel spacin g (khz) x chan + 87 .0 mhz band = 1 or 2 frequency = channel spacing (khz) x chan + 76.0 mhz band = 3 frequency = channel spacing (khz) x chan + 6 5 .0 mhz chan is updated after a seek operation. 0x00 5 direct mode directly control mode, only used when test. 0 4 tune t une 0 = disable 1 = enable the tune operation begins when the tune bit is set high. the stc bit is set high when the tune operation completes. the tune bit is reset to low automatically when the tune operation completes.. 0 3: 2 band[1:0] ban d select. 00 = 87 ? 108 mhz (us/europe) 01 = 76 ? 91 mhz (japan) 10 = 76 ? 108 mhz ( world wide) 11 1 0 0 = 65 ? 76 m h z east europe o r 50 - 6 5 m hz 1: 0 space [1:0] channel spacing. 00 = 100 khz 01 = 200 khz 10 = 50khz 11 = 25khz 0 0 04h 15 rsvd reserved 0 14 stcien seek/tune complete interrupt enable. 0 = d i sab l e i n t er r u p t 1 = enable interrupt se t t i n g st c i en = 1 w i l l g en er at e a l o w p u l se o n gpio2 when the interrupt occurs. 0 13:12 rsvd reserved 00 11 de de - emphasis. 0 = 75 s; 1 = 50 s 0 10 rsvd reserved 9 softmute_en if 1, softmute enable 1 8 afcd afc disable. if 0, afc work; 0 1 if 0x07h_bit<9> ( band )=1, 65 - 76mhz; =0, 50 - 76mhz
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 11 of 23 reg bits name function default if 1, afc disabled. 7 rsvd reserved 6 i2s_enabled i2s bus enable if 0, disabled; if 1, enabled. 0 5:4 gpio3[1:0] general purpose i/o 3. 00 = high impedance 01 = mono/stereo indicator (st) 10 = low 11 = high 00 3:2 gpio2[1:0] general purpose i/o 2. 00 = high impedance 01 = in terrupt (int) 10 = low 11 = high 00 1:0 gpio1[1:0] general purpose i/o 1. 00 = high impedance 01 = reserved 10 = low 11 = high 00 05h 15 int _mode if 0, generate 5ms interrupt; i f 1 , i nt e r r upt l a s t unt i l r e a d r e g0 c h a c t i on occurs. 1 14:12 rsvd reserve d 000 1 1 :8 seekth[3 :0] 2 s eek s n r t hr e s hol d v a l ue 1000 7:6 lna_port_sel[1:0] lna input port selection bit: 10: fmin 10 5:4 rsvd resvered 0 0 3:0 volume[3:0] dac gain control bits (volume). 0000=min; 1111=max volume scale is logarithmic when 0000, ou tput mute and output impedance is very large 1111 06h 15 rsvd reserved 0 14 :13 o p e n_ m o de [ 1: 0 ] open reserved register mode. 11=open behind registers writing function others: only open behind registers reading function 0 0 12 i2s_mode 3 if 0, master mode ; if 1, slave mode. 0 11 sw_lr ws relation to l/r channel. 3 if 0, ws=0 - >r, ws=1 - >l; if 1, ws=0 - >l, ws=1 - >r. 10 10 sclk_i_edge when i2s enable 3 if 0, use normal sclk internally; 0 2 this value is snr threshold for seeking, and the default value 1000 is about 32db snr. 3 this function is open when i2s_enabled=1.
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 12 of 23 reg bits name function default if 1, inverte sclk internally. 9 data_signed if 0, i2s output unsi gned 16 - bit audio data. 3 if 1, i2s output signed 16 - bit audio data. 0 8 ws_i_edge if 0, use normal ws internally; 3 if 1, inverte ws internally. 0 7:4 i2s_sw_cnt[4:0] o n l y val i d 3 i n m ast er m o d e 4'b1000: ws_step_48; 4'b0111: ws_step=44.1kbps; 4'b0110: ws_step=32kbps; 4'b0101: ws_step=24kbps; 4'b0100: ws_step=22.05kbps; 4'b0011: ws_step=16kbps; 4'b0010: ws_step=12kbps; 4'b0001: ws_step=11.025kbps; 4'b0000: ws_step=8kbps; 0000 3 sw_o_edge if 1, invert ws output when as master. 3 0 2 sclk_o_edge if 1, invert sclk output when as master. 3 0 1 l_dely if 1, l channel data delay 1t. 3 0 0 r_dely if 1, r channel data delay 1t. 3 0 07h 15 rsvd reserved 0 14:10 th_sofrblend[5:0] threshold for noise soft blend setting, unit 2db 10000 9 65m_50m mode valid w hen band[1:0] = 2?b11 (0x03h_bit<3:2>) 1 = 65~76 mhz; 0 = 50~76 mhz. 1 8 rsvd reserved 0 7:2 seek_th _old 4 seek threshold for old seek mode , valid when seek_mode=001 000000 1 softblend_en if 1, softblend enable 1 0 freq_mode if 1, then freq setting changed. freq = 76000(or 87000) khz + freq_direct (08h) khz. 0 0ah 15 rdsr rds ready 0 = no rds/rbds group ready(default) 1 = new rds/rbds group ready 0 14 stc seek/tune complete. 0 = not complete 1 = complete the seek/tune complete flag is set when the seek or tune operation completes. 0 13 sf seek fail. 0 = seek successful; 1 = seek failure the seek fail flag is set when the seek operation fails to find a channel with an rssi level greater than seekth[5:0] . 0 12 rdss rds synchronization 0 = rds dec oder not synchronized(default) 0 4 0x20h_bit<14:12>, seek_mode register . default value is 000; when = 001, will add the 5807sp seek mode.
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 13 of 23 reg bits name function default 1 = rds decoder synchronized available only in rds verbose mode 11 blk_e when rds enable: 1 = block e has been found 0 = no block e has been found 0 10 st stereo indicator. 0 = mono; 1 = stereo stereo indication is avai lable on gpio3 by setting gpio 3 [1:0] =01. 1 9:0 readchan[9:0] read channel. band = 0 frequency = channel spacing (khz) x readchan[9:0]+ 87.0 mhz band = 1 or 2 frequency = channel spacing (khz) x readchan[9:0]+ 76.0 mhz band = 3 frequency = channel spacin g (khz) x readchan[9:0]+ 65.0 mhz readchan[9:0] is updated after a tune or seek operation. 8?h00 0bh 15:9 rssi[6:0] rssi. 000000 = min 111111 = max rssi scale is logarithmic. 0 8 fm true 1 = the current channel is a station 0 = the current channel is n ot a station 0 7 fm_ready 1=ready 0=not ready 0 <6:5> reserved 0 <4> a bcd _ e 1= the block id of register 0ch,0dh,0eh,0fh is e 0= t h e b l o ck i d o f r eg i st er 0ch , 0d h , 0eh , 0f h i s a, b, c, d <3:2> blera[1:0] block errors level of rds_data_0, and is a lways read as errors level of rds block a (in rds mode) or block e (in rbds mode when abcd_e flag is 1) 00= 0 errors requiring correction 01= 1~2 errors requiring correction 10= 3~5 errors requiring correction 11= 6+ errors or error in checkword, correctio n not possible. available only in rds verbose mode <1:0> blerb[1:0] block errors level of rds_data_1, and is always read as errors level of rds block b (in rds mode ) or e (in rbds mode when
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 14 of 23 reg bits name function default abcd_e flag is 1). 00= 0 errors requiring correction 01= 1~2 e rrors requiring correction 10= 3~5 errors requiring correction 11= 6+ errors or error in checkword, correction not possible. available only in rds verbose mode 0ch <15:0> rdsa[15:0] block a ( in rds mode) or block e (in rbds mode when abcd_e flag is 1) 1 6 ? h5803 0dh <15:0> rdsb[15:0] block b ( in rds mode) or block e (in rbds mode when abcd_e flag is 1) 16 ? h5804 0eh <15:0> rdsc[15:0] block c ( in rds mode) or block e (in rbds mode when abcd_e flag is 1) 16 ? h5808 0fh <15:0> rdsd[15:0] block d ( in rds mo de) or block e (in rbds mode when abcd_e flag is 1) 16 ? h5804
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 15 of 23 8 pin s description figure 8 - 1 . RDA5807FP top view table 8 - 1 RDA5807FP sop16 pins description symbol pin description gnd 2 , 5,6,11,14 ground. connect to ground plane on pcb rf gnd 3 rf ground. connect to rf ground plane to pcb fmin 4 fm single input rclk 9 32.768khz reference clock input vdd 10 p ow er su ppl y lout,rout 13,12 right/left audio output sclk 7 clock input for serial control bus sda 8 d ata inp ut/output for serial control bus gpio1,gpio2,gpio3 1 ,16, 1 5 general purpose input/output rds 5807 fp sop 16 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gp io2 gp io3 gnd rout l out rcl k vd d gnd gp io1 gnd rf g nd f m in gnd gnd sc lk sd a
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 16 of 23 table 8 - 2 internal pin configuration symbol pin description fmin 4 fmin fms mn1 rload 50 pf rclk 9 rclk 5 m 20 pf 6 pf inv 5 m 0 x 02 h _ bit<10> vdd = 1 =0 sclk/sdio 7/8 47 k s in s out mn 1 sdio \sclk gpio1/gpio2/gpio3 1/16/15 gpio1 \2\ 3 in out 200 k vdd
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 17 of 23 9 application d iagram 9.1 RDA5807FP common application : RDA5807FP sop16 gpio1 gnd rf gnd fmin gnd gnd sclk sda gpio2 gpio3 gnd rout lout rclk vdd gnd j 1 c3 4. 7uf c4 4. 7uf 32 . 768khz l 1 100 nh c2 24pf v1 c1 22 nf sclk sda f1 1.5k@100mhz f 2 1.5k@100 mhz u1 c7 100pf esd f igure 9 - 1 . RDA5807FP f m t uner a p pl i c at i on d i a gr a m ( t c x o a ppl i c at i on ) 9.1.1 bill of materials: co mponent value de s cri p t ion supplier u1 r da5807fp sop16 b r oadc as t f m radio tuner rda j1 c om m on 32 r es i s t anc e h ead p hon e l1/ c 2 100nh/2 4 pf lc c h oc k f or f mi n i np ut mur at a c4,c5 125 f au d i o a c c o upl e c a p ac i t or s murata c1 22nf p o w er s u pp l y b y p as s c apac itor murata c7 100pf a c c o up l e c ap ac itors mur at a esd tvs f 1/f2 1. 5k @ 1 00 mh z f m b a nd f er r i t e murata notes: 1. j 1 : c om mon 32 ? r es i s t anc e h eadph one ; 2 . v 1: p ow er s up pl y ( 2 .7 ~ 3.3 v); 3 . f m c hok e ( l 1 and c 2 ) for audio common and lna input c ommon ; 4 . p l ac e c 1 c l os e t o 5807np pin 10.
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 18 of 23 10 physical dimension figure 10 - 1 illustrates the package details for the RDA5807FP . the package is lead - free and rohs - compliant.
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 19 of 23 figure 10 - 1. 16 pin sop pcb land pattern 11 pcb land pattern fig ure 1 1 . classification reflow profile profile feature sn - pb eutectic assembly pb - free assembly average ramp - up rate (t smax to t p 3 ) o 3 c/second max. o c/second max. preheat - temperature min (t smin - temperature max (t ) s max - time (t ) smin to t smax ) 100 o 100 c o 60 - 120 seconds c 150 o 200 c o 60 - 180 seconds c time maintained above: - temperature (t l - time (t ) l ) 183 o 60 - 150seconds c 217 o 60 - 150 seconds c p eak / c l assi f i ca t i on temperature(t p see table - ii ) see table - iii time within 5 o c o f act u al p eak t e m pe r at u r e ( t p 10 - 30 seconds ) 20 - 40 seconds ramp - down rate 6 o 6 c/second max. o c/seconds max. time 25 o 6 minutes max. c to peak 8 minutes max.
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 20 of 23 temperature table - i classification reflow profiles package thickness volume mm <350 3 volume mm 350 3 2.5mm 240 + 0/ - 5 o 225 + 0/ - 5 c o c 2.5mm 225 + 0/ - 5 o 225 + 0/ - 5 c o c table ? ii snpb eutectic process ? package peak reflow temperatures p ackage thickness volume mm 350 3 volume mm 350 - 2000 3 volume mm 2000 3 1.6mm 260 + 0 o 260 + 0 c * o 260 + 0 c * o c * 1.6mm ? 2.5mm 260 + 0 o 250 + 0 c * o 245 + 0 c * o c * 2.5mm 250 + 0 o 245 + 0 c * o 245 + 0 c * o c * * t ol er an ce : t he dev i ce m anu f ac t ur e r / su ppl i er sh al l assu r e pr o ce ss co m p at i bi l i t y up t o and including the stated classification temperature(this mean peak reflow temperature + 0 o c. for example 260+ 0 o c ) at the rated msl level. t abl e ? ii i p b - f r ee p r ocess ? p ackage c l assi f i cat i on r e f l o w t em per at u r es note 1: all temperature refer topside of the package. m easured on the package body surface. note 2: the profiling tolerance is + 0 o c , - x o i s r e q ui r ed t o c ont r ol t he pr o f i l e pr o ce s s but a t no t i m e w i l l i t ex ce ed - 5 c (based on machine variation ca pabi l i t y ) w hat ev er o note 3: package volume excludes external terminals(balls, bumps, lands, leads) and/or non integral heat sinks. c . t he producer assures proces s compatibility at the peak reflow profile temperatures defined in table ? iii. note 4: the maximum component temperature reached during reflow de pends on package the thickness and volume. the use of convection reflow processes reduces the thermal gradients between packages. however, thermal gradients due to differences in thermal mass of smd pack age may sill exist. note 5: components intended for use in a ? lead - free ? assembly process shall be evaluated using the ? lead free ? classification temperatures and profiles defined in table - i ii iii whether or not lead free.
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 21 of 23 rohs compliant the product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (pbb) or polybrominated diphenyl ethers (pbde) , and are therefore considered rohs compliant. esd sensitivity integrated circuits are esd sensitive and can be damaged by static electricity. proper esd techniques should be used when handling these devices.
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 22 of 23 12 change list rev date auther change description v 1.0 20 11 - 0 7 - 18 chun zhao , yanan liu original d raft .
r d a mi c r o el ec t r o ni c s , i nc . rd a 5807n p f m t uner v 1. 2 t he i n f or m at i on c ont ai ned her ei n i s t he ex c l us i v e pr oper t y of rda an d s hal l no t be di s t r i but ed, r epr oduc ed, or di s c l o s ed i n w hol e or i n part without prior written permission of rda . page 23 of 23 contact information rda m icroelectronics ( shanghai), inc. suite 1108 block a, e - wing center, 113 zhichun road haidian district, beijing te l : 86 - 10 - 6 263 536 0 f ax : 86 - 10 - 8 261 266 3 postal code: 100086 suite 302 building 2, 690 bibo road pudong district, shanghai te l : 86 - 21 - 5 0271 10 8 f ax : 86 - 21 - 5 027 109 9 postal code: 201203 copyright ? rda microelectronics inc. 2006. all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

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